PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a PLD that implements a decreased circuit area and an increased operating speed.SOLUTION: A circuit configuration is such that gates of transistors disposed between input and output terminals of a programmable switch element are in an electrically floating state during a period when a signal is input into the programmable switch element. The configuration enables a boosting effect of stepping up gate voltages to act on a signal flowing between programmable logic elements in keeping an amplitude voltage intact, to whereby decrease a circuit area by a size occupied by a step-up circuit such as a pull-up circuit and increase an operating speed.