INFORMATION PROCESSING APPARATUS AND DEBUGGING METHOD

摘要

An information processing apparatus includes a system memory, a cache system that includes a cache memory, and a plurality of cores, each of which accesses the system memory and the cache memory. The cache system stores in a cache line of the cache memory a break indicator that designates one or more of the plurality of cores. The cache system determine whether a first core in the plurality of cores that issues a request to read data from an address that corresponds to the cache line in which the break indicator is stored matches one of the cores designated by the break indicator. If the first core matches one of the cores designated by the break indicator, the cache system returns a break command to the first core. If the first core does not match one of the cores designated by the break indicator, the cache system returns the data to the first core.

主权项

1. An information processing apparatus comprising:
a system memory; a cache system including a cache memory; and a plurality of cores, each of which accesses the system memory and the cache memory, wherein the cache system stores in a cache line of the cache memory a break indicator that designates one or more of the plurality of cores, and is configured to: determine whether a first core in the plurality of cores that issues a request to read data from an address that corresponds to the cache line in which the break indicator is stored, matches one of the cores designated by the break indicator; and responsive to the determining, return a break command to the first core if the first core matches one of the cores designated by the break indicator, and return the data to the first core if the first core does not match one of the cores designated by the break indicator.