EFFICIENT HARDWARE INSTRUCTIONS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSORS
摘要
<p>A method and apparatus for efficiently processing data in various formats in a single instruction multiple data ("SIMD") architecture is presented. Specifically, a method to unpack a fixed-width bit values in a bit stream to a fixed width byte stream in a SIMD architecture is presented. A method to unpack variable-length byte packed values in a byte stream in a SIMD architecture is presented. A method to decompress a run length encoded compressed bit-vector in a SIMD architecture is presented. A method to return the offset of each bit set to one in a bit-vector in a SIMD architecture is presented. A method to fetch bits from a bit-vector at specified offsets relative to a base in a SIMD architecture is presented. A method to compare values stored in two SIMD registers is presented.</p>
申请公布号
WO2014150913(A2)
申请公布日期
2014.09.25
申请号
WO2014US24523
申请日期
2014.03.12
申请人
ORACLE INTERNATIONAL CORPORATION
发明人
GANESH, AMIT;CHAVAN, SHASANK K.;MARWAH, VINEET;KAMP, JESSE;PATTHAK, ANINDYA C.;GLEESON, MICHAEL J.;HOLLOWAY, ALLISON L.;MACNICOL, ROGER