| 发明名称 |
DUAL-STRUCTURE CLOCK TREE SYNTHESIS (CTS) |
| 摘要 |
Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of the upper-level clock tree to a set of clock sinks. The lower-level clock tree can be optimized to reduce latency, power consumption, and/or area. |
| 申请公布号 |
US2014289694(A1) |
申请公布日期 |
2014.09.25 |
| 申请号 |
US201414221139 |
申请日期 |
2014.03.20 |
| 申请人 |
Synopsys, Inc. |
发明人 |
Ma Xiaojun;Pan Min;Cao Aiqun;Ding Cheng-Liang |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A method for clock tree synthesis, the method comprising:
constructing a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree, and wherein each upper-level clock tree is optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew; and for each leaf of each upper-level clock tree, constructing a lower-level clock tree, wherein the lower-level clock tree distributes a clock signal from the leaf of the upper-level clock tree to a set of clock sinks, and wherein the lower-level clock tree is optimized to reduce latency, power consumption, and/or area. |
| 地址 |
Mountain View CA US |
