| 主权项 |
1. A memory device comprising:
an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated read word line, each column of memory cells forming at least one column group, and the memory cells of each column group being coupled to an associated read bit line, each column group having an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where said read operation cannot be performed; precharge circuitry configured, for each column group in said active mode of operation, to precharge the associated read bit line to a first voltage level prior to said read operation; each memory cell comprising coupling circuitry connected between the associated read bit line and a second voltage level different to said first voltage level, during said read operation the coupling circuitry associated with the activated memory cell being configured to selectively discharge the associated read bit line towards the second voltage level dependent on a data value stored within that activated memory cell; and the memory device further comprising clamping circuitry configured, for each column group in said non-active mode of operation, to connect the associated read bit line to said second voltage level, in order to remove a leakage current path through the coupling circuitry of each memory cell of that column group. |
