发明名称 |
LATCH CIRCUIT OF DISPLAY APPARATUS, DISPLAY APPARATUS, AND ELECTRONIC EQUIPMENT |
摘要 |
A latch circuit for outputting data for M pixels present in one line on a display panel in a time-division manner for each pixel, in order to drive each pixel from among the M pixels based on N-bit data, includes M×N 1-bit latch circuits in which N 1-bit latch circuits are arranged in the column direction Y and M 1-bit latch circuits are arranged in the row direction X, each circuit latching 1-bit data. Each 1-bit latch circuit includes a data latch unit circuit that latches data corresponding to any one bit of the N bits at different timings for each row, a line latch unit circuit that simultaneously latches data from the data latch unit circuit in each row, and an output enable element that outputs data from the line latch unit circuit based on an enable signal for selecting any one column. |
申请公布号 |
US2014285405(A1) |
申请公布日期 |
2014.09.25 |
申请号 |
US201414175437 |
申请日期 |
2014.02.07 |
申请人 |
SEIKO EPSON CORPORATION |
发明人 |
NOMURA Takeshi |
分类号 |
G09G5/00 |
主分类号 |
G09G5/00 |
代理机构 |
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代理人 |
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主权项 |
1. A latch circuit of a display apparatus for outputting data for M pixels (M is an integer of 2 or more) present in one line on a display panel in a time-division manner for each pixel, in order to drive each pixel from among the M pixels based on N-bit data (N is an integer of 2 or more), comprising:
M×N 1-bit latch circuits in which N 1-bit latch circuits are arranged in a column direction and M 1-bit latch circuits are arranged in a row direction, each circuit latching 1-bit data; wherein each of the M×N 1-bit latch circuits includes a data latch unit circuit that latches data corresponding to any one bit of the N bits at different timings for each row, a line latch unit circuit that simultaneously latches data from the data latch unit circuit in each row, and an output enable element that outputs data from the line latch unit circuit based on an enable signal for selecting any one column. |
地址 |
Tokyo JP |