CURRENT-MODE D LATCH WITH RESET FUNCTION AND ASSOCIATED CIRCUIT

摘要

A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

主权项

1. A current-mode D latch, comprising:
a first load element connected between a power supply voltage and a node x, wherein the node x generates an output signal; a second load element connected between the power supply voltage and a node y, wherein the node y generates an inverted output signal; a first stage circuit comprising a first transistor, a second transistor and a third transistor, wherein the first transistor has a drain terminal connected with the node x, a gate terminal receiving an inverted input signal and a source terminal connected with a node a, wherein the second transistor has a drain terminal connected with the node y, a gate terminal receiving an input signal and a source terminal connected with the node a, wherein the third transistor has a drain terminal connected with the node a, a gate terminal receiving an inverted clock signal and a source terminal connected with a node c; a second stage circuit comprising a fourth transistor, a fifth transistor and a sixth transistor, wherein the fourth transistor has a drain terminal connected with the node x, a gate terminal connected with the node y and a source terminal connected with a node b, wherein the fifth transistor has a drain terminal connected with the node y, a gate terminal connected with the node x and a source terminal connected with the node b, wherein the sixth transistor has a drain terminal connected with the node b, a gate terminal receiving a clock signal and a source terminal connected with the node c; a bias current source connected between the node c and a ground voltage; a first switch transistor connected between the power supply voltage and the node c, and controlled by an inverted reset signal; and a second switch transistor connected between the node x and the ground voltage, and controlled by a reset signal.