Through Silicon Via with Embedded Barrier Pad

摘要

A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.

主权项

1. A method, comprising:
providing an electrically insulating substrate with a via; forming a metal bottom through substrate via (TSV) pad in the via, the bottom TSV pad having a top surface less than about 6 microns below a target surface of the substrate; depositing a metal barrier pad in the via and on the top surface of the bottom TSV pad, wherein the top surface of the metal barrier pad is below the target surface of the substrate; and depositing a metal top TSV pad on the top surface of the metal barrier pad, where the top surface of the metal top TSV pad is about level with the target surface of the substrate; wherein the metal top TSV pad, the metal barrier pad and the metal bottom TSV pad completely fill the via.