| 摘要 |
A system and method according to the present disclosure includes a master device, a bus interface link, and a slave device. The master device includes a power supply and a detection unit which detects the impedance of the power supply. An inverter supplies a first path to the power supply on a first terminal of a clock signal. Further, the inverter supplies a second path to a first ground line on a second terminal of the clock signal. The bus interface link combines the master device with the slave device. Additionally, a bidirectional communication line is combined with the bus interface link. A gating component supplies a second ground line to the power supply along the first path. Furthermore, a receiver determines a bit value from a plurality of clock data signals transmitted from the master device. |
