发明名称 A combinatorial circuit and method of operation of such a combinatorial circuit
摘要 An integrated level shifting combinatorial circuit, and method of operation for receiving two or more input signals (A,B,CK) associated with a first voltage domain VDDP and performing a combinatorial operation to generate an output signal WL associated with a second voltage domain VDDC. A first combinatorial circuit portion 110-130, 170 operates at a first voltage whilst a second combinatorial circuit portion 140-200 operates at a second voltage VDDC. The second combinatorial circuit portion comprises an output node identifying a value of the output signal WL. The second combinatorial circuit portion includes feedback circuitry 185, 220 which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. Also contention mitigation circuitry 210 operating in the second voltage domain is used to reduce the voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry's performance of the combinatorial operation based on the received input signals causes the combinatorial circuitry to switch the voltage on the output node. The contention mitigation circuitry therefore assists the combinatorial circuitry in performing the required voltage switching on the output node. This provides a particularly performance and power consumption efficient mechanism for performing the combinatorial operation and can be used to perform a relatively large level shifting between the first and second voltage domains. The circuit is suitable for use in a word line driver (figure 2). A claim for storage medium for storing a memory compiler program is also disclosed.
申请公布号 GB2512187(A) 申请公布日期 2014.09.24
申请号 GB20140000925 申请日期 2014.01.20
申请人 ARM LIMITED 发明人 GUS YEUNG;SRINIVASAN SRINATH;FAKHRUDDIN ALI BOHRA
分类号 G11C8/08;H03K19/0175;H03K19/0185;H03K19/0948 主分类号 G11C8/08
代理机构 代理人
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