| 摘要 |
The present invention relates to a system for synchronizing port entries to a low-power state. A device according to an embodiment of the present invention includes: transmission logic; reception logic; and power logic which switches the transmission logic and the reception logic to a low power state. The power logic halts the high-speed data transmission rate state of the transmission logic and the reception logic of the device and switches the transmission logic and the reception logic to a power-saving state. |
