| 摘要 |
In a multicore system in which a plurality of CPUs each including a cache memory share one main memory, a write buffer having a plurality of stages of buffers each holding data to be written to the main memory and an address of a write destination is provided between the cache memory and the main memory, and at the time of a write to the write buffer from the cache memory, an address of a write destination and the addresses stored in the buffers are compared, and when any of the buffers has an agreeing address, data is overwritten to this buffer, and the buffer is logically moved to a last stage. |
