发明名称 Method of estimating an exposure tolerance and method of manufacturing a semiconductor device
摘要 <p>According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions (R) along a first surface (100a) of a substrate (100). The method can form a plurality of patterns (PT1a, PT1b, PT1c, PT1d, PT1e) for estimation by performing exposure on each of the regions (R) using at least three levels of exposure condition using an exposure mask (M1). The method can measure dimensions of the patterns (PT1a, PT1b, PT1c, PT1d, PT1e) for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions (R). In the first region (R), a first dimension of a first pattern (PT1a, PT1b, PT1c, PT1d, PT1e) for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.</p>
申请公布号 EP2781960(A1) 申请公布日期 2014.09.24
申请号 EP20130184534 申请日期 2013.09.16
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YAMANE, OSAMU;MASUKAWA, KAZUYUKI;KAI, YASUNOBU
分类号 G03F7/20 主分类号 G03F7/20
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