发明名称 |
DIGITAL PHASE-LOCKED LOOP USING PHASE-TO-DIGITAL CONVERTER, METHOD THEREOF, AND DEVICES HAVING THE SAME |
摘要 |
<p>Disclosed are a digital phase-locked loop (DPLL) circuit using a phase-to-digital converter, a method for operating the same, and an apparatus comprising the same. The DPLL comprises a digital control oscillator changing a frequency and a phase of an output oscillation signal in response to a digital control code; a main frequency divider dividing a frequency of the output oscillation signal to generate a first feedback signal; and a phase-to-digital converter dividing the phase of the output oscillation signal and generating a quantization code acquired by converting the phase difference between a reference signal and the first feedback signal into a digital value by using the divided phase signal, wherein the digital control code is generated based on the quantized code.</p> |
申请公布号 |
KR20140113216(A) |
申请公布日期 |
2014.09.24 |
申请号 |
KR20130028321 |
申请日期 |
2013.03.15 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JANG, TAE KWANG;LIUJENLUNG;XINGNAN;PARK, JAE JIN |
分类号 |
H03L7/08;H03L7/099 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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