| 摘要 |
<p>A PLL circuit includes a divider configured to generate a divided signal having a cycle of T/M (where M is an integer greater than or equal to two) by dividing an oscillation signal; a phase comparator configured to generate a phase comparison result by calculating an exclusive logical OR of M reference signals and the divided signal, the M reference signals having the cycle of T and respective time intervals shifted sequentially by T/2M; a loop filter configured to generate a voltage signal using the phase comparison result as input; and a voltage-controlled oscillator configured to generate the oscillation signal by oscillating at a frequency depending on the voltage signal.</p> |
