发明名称 CIRCUIT, CONTROL SYSTEM, CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH PROGRAM IS RECORDED
摘要 <p>In order to provide a circuit which can realize high-speed frequency tracking performance while satisfying jitter/wander suppression performance, the circuit controls loop gain of a PLL means, which extracts a clock signal of a SDH signal or an Ethernet signal from an OTN signal, on the basis of a result of processing a jitter/wander component and a frequency change state on the basis of phase comparison data of the PLL means.</p>
申请公布号 EP2395666(A4) 申请公布日期 2014.09.24
申请号 EP20100755981 申请日期 2010.03.15
申请人 NEC CORPORATION 发明人 TAKAHASHI, MASAYUKI;YOSHIHARA, TOMOKI
分类号 H03L7/107;H03L7/08;H03L7/093 主分类号 H03L7/107
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