Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods

摘要

A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.

主权项

1. A method of fabricating a metal-insulator-semiconductor field-effect transistor (MISFET), the method comprising:
providing a silicon carbide SiC layer having source and drain regions of a first conductivity type spaced apart therein, the SiC layer comprising a carbon (C)-face; implanting first conductivity type impurity atoms between the spaced apart source and drain regions in the SiC layer to form a buried channel region; providing a gate insulation layer directly on the C-face of the SiC layer between the source and drain regions, the gate insulation layer comprising silicon; oxidizing the gate insulation layer to form a silicon dioxide layer that forms a distinct interface along the C-face of the SiC layer that generates a fixed net charge that is the same polarity as majority carriers of the source region and depletes majority charge carriers from an adjacent portion of the buried channel region, wherein oxidizing the gate insulation layer forms the distinct interface along the C-face of the SiC layer configured so that a product of a concentration of the first conductivity type impurity atoms in a per unit area and thickness of the buried channel region is equal to or less than an amount of fixed charge per unit area provided by the silicon dioxide layer; and providing a gate contact on the silicon dioxide layer over the buried channel region of the SiC layer between the source and drain regions.