Low clock energy double-edge-triggered flip-flop circuit

摘要

A double-edge-triggered flip-flop circuit and a method for operating the double-edge-trigger flip-flop circuit are provided. Sub-circuits of a flip-flop circuit are coupled to a ground supply and decoupled the sub-circuits from a power supply when a clock signal is asserted. The sub-circuits generate trigger signals including a first pair of signals and a second pair of signals. The first pair of signals is evaluated, levels of the second pair of signals are maintained when the clock signal is asserted, and an output signal is transitioned to equal an input signal based on the trigger signals when the clock signal is asserted.

主权项

1. A method, comprising:
coupling sub-circuits of a flip-flop circuit to a ground supply and decoupling the sub-circuits from a power supply when a clock signal is asserted, wherein the sub-circuits are configured to generate trigger signals including a first pair of signals and a second pair of signals; evaluating the first pair of signals generated by the sub-circuits when the clock signal is asserted; maintaining levels of the second pair of signals when the clock signal is asserted; transitioning an output signal to equal an input signal based on the trigger signals when the clock signal is asserted; and transitioning the output signal to equal the input signal based on the trigger signals when the clock signal is negated.