Programmable memory with skewed replica and redundant bits for reset control

摘要

Embodiments of a circuit and method for setting initial trim bits in an integrated circuit (IC) are described. The circuit includes a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of the IC following energizing of the IC. The memory array further includes replica bit circuitry to generate a number of replica bits. A logic circuit coupled to the memory array and the main circuit of the IC is configured to receive the replica bits, and to provide a signal to the IC that indicates when the trim bits are valid. In one embodiment, the circuit further includes redundancy check logic configured to receive a number of the trim bits from the memory array, compare the number of trim bits to a pre-determined or computed value, and to provide a BITS_OK signal to the logic circuit.

主权项

1. An initial trim circuit comprising:
a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of an integrated circuit (IC) including the initial trim circuit following energizing of the IC, the memory array comprising replica bit circuitry to generate a number of replica bits, wherein the replica bit circuitry is configured to generate the number of replica bits using a current through the replica bit circuitry skewed relative to a current through the plurality of trim bit cells; and a logic circuit coupled to the memory array and the IC, the logic circuit configured to receive the number of replica bits and to provide a signal to the main circuit of the IC that indicates when the trim bits are valid.