Information processing device, arithmetic processing method, and electronic apparatus

摘要

An information processing device includes: plural input registers including a first input register and a second input register; an added value register; a first adding unit that performs addition processing for stored data of the first input register and stored data of the second input register; a second adding unit that performs addition processing for connected data, which is obtained by connecting the stored data of the first input register and the stored data of the second input register, and stored data of the added value register; and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers.

主权项

1. An information processing device comprising:
plural input registers including a first input register, a second input register, a third input register, and a fourth input register; a first adding unit that performs addition processing for stored data of the first input register and stored data of the third input register; a second adding unit that performs addition processing for first connected data, which is obtained by connecting the stored data of the first input register as lower-order data and stored data of the second input register as higher-order data, and second connected data, which is obtained by connecting the stored data of the third input register as lower-order data and stored data of the fourth input register as higher-order data; a third adding unit that performs addition processing for the stored data of the second input register and the stored data of the fourth input register; and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers, the plural output registers include a register in which a processing result of the third adding unit is stored, and in each of the execution cycles, the first adding unit stores the processing result of the first adding unit in any one of the plural output registers, the second adding unit stores the processing result of the second adding unit in any one of the plural output registers, and the third adding unit stores the processing result of the third adding unit in any one of the plural output registers.