Power management domino SRAM bit line discharge circuit

摘要

A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.

主权项

1. A method for operating a domino static random access memory (SRAM) comprising:
precharging a local bit line, the local bit line being connected to an SRAM cell; precharging a global bit line to a precharge voltage; and reading data from the SRAM, the reading further comprising: a “zero” data value stored in the SRAM cell driving the local bit line to a discharged level, the local bit line discharged level enabling a global bit line discharge logic to discharge the global bit line to a voltage level between the precharge voltage level and a voltage above ground, and wherein the global bit line discharge logic is a P-Channel Field-effect transistor (PFET) transistor having a drain connected to a ground, a source connected to the global bit line, and a gate connected to the local bit line, and the PFET transistor drawing the global bit line to one PFET threshold above ground.