发明名称 INTEGRATED CIRCUIT DEVICE AND METHOD OF CREATING MASK LAYOUT
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit device which suppresses occurrence of defects of wiring even when micronized and a method of creating a mask layout.SOLUTION: A method of creating a mask layout is for creating a mask layout of an exposure mask used in forming wiring of an integrated circuit device and includes a step of estimating the shape of wiring to be formed according to an edge of a pattern contained an initial layout of the exposure mask and a step of correcting the shape of the edge when the estimated shape of wiring does not meet requirements.
申请公布号 JP2014174288(A) 申请公布日期 2014.09.22
申请号 JP20130046012 申请日期 2013.03.07
申请人 TOSHIBA CORP 发明人 OKADA MOTOHIRO;SODA SHUHEI;HASHIMOTO TAKAKI;KAI YASUNOBU;MASUKAWA KAZUYUKI;KONO YUKO;KODAMA CHIKAAKI;UNO TAIGA;MASHITA HIROMITSU
分类号 G03F1/70;H01L21/027 主分类号 G03F1/70
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