| 摘要 |
The present invention relates to a network processor including a network reference clock processor module for substantially providing a low jitter reference signal or a low-wander reference signal. According to one or more embodiments, the network reference clock processor module includes a digital phase locked loop configured to substantially attenuate a wander noise portion from a reference signal. In addition, the network reference clock processor module includes an analog phase locked loop communicatively coupled to the digital phase locked loop and is configured to receive the reference signal from the digital phase locked loop. The analog phase locked loop is configured to attenuate a jitter noise portion having a first frequency characteristic from the reference signal and to provide the reference signal to a transceiver communicatively coupled to the analog phase locked loop. The transceiver is configured to attenuate a jitter noise portion having a second frequency characteristic from the reference signal. |
