发明名称 Serial Protocol for Agile Sample Rate Switching
摘要 The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
申请公布号 US2014270122(A1) 申请公布日期 2014.09.18
申请号 US201414291696 申请日期 2014.05.30
申请人 Agere Systems LLC 发明人 Lau King-Hon;Ransjin Johannes G.;Simmonds Harold T.;Yoder James D.
分类号 H04M3/00 主分类号 H04M3/00
代理机构 代理人
主权项 1. A communication circuit for communicating data across a transmission medium at two or more communication rates, the communication circuit comprising: a variable-rate interface circuit adapted to transmit or receive signals via the transmission medium at an interface clock rate that is (i) about equal to an approximate common multiple of the two or more communication rates and (ii) not equal to an exact common multiple of the two or more communication rates.
地址 Allentown PA US
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