| 摘要 |
<p>Provided are a test method, device and system for a system on chip (SoC) chip. The system comprises: an STC (101), a bus (102) and a peripheral interface (103), wherein the STC (101) is connected to each subsystem of the SoC chip through the bus (102); and the STC (101) receiving the start and end addresses of a test vector configured by an off-chip test terminal through the peripheral interface (103), acquiring the test vector according to the start and end addresses, and executing the test vector so as to obtain test results of corresponding subsystems.</p> |
