| 摘要 |
PROBLEM TO BE SOLVED: To suppress a reduction in access speed due to a data bus inversion circuit.SOLUTION: A semiconductor device includes a data bus that is provided between a memory cell array 11 and a data input/output terminal 24. On a path of the data bus, the following are included: switching circuits 50 to 57 that assign a plurality of data pieces to either one of the data bus or another data bus; DBI circuits 60 to 67 that invert or non-invert the plurality of data pieces; and BOC circuits 70 to 77 that switch a correspondence relation between a plurality of wirings that are included in the data bus and the plurality of data pieces. The DBI circuits 60 to 67 are connected to the data input/output terminal 24 through at least either ones of the switching circuits 50 to 57 or BOC circuits 70 to 77 on the path of the data bus. According to this invention, an access delay due to the operation of the DBI circuits 60 to 67 can be concealed in the operation time of another circuit. |
