| 发明名称 |
Digital Period Divider |
| 摘要 |
A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter. |
| 申请公布号 |
US2014270048(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201414200317 |
申请日期 |
2014.03.07 |
| 申请人 |
Microchip Technology Incorporated |
发明人 |
Julicher Joseph;Kilzer Kevin;Eeden Cobus Van |
| 分类号 |
H03K23/00 |
主分类号 |
H03K23/00 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A digital period divider comprising:
a first counter comprising R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits comprising a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter. |
| 地址 |
Chandler AZ US |
