发明名称 |
NONVOLATILE MEMORY CELLS AND METHODS OF MAKING SUCH CELLS |
摘要 |
A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed. |
申请公布号 |
US2014264552(A1) |
申请公布日期 |
2014.09.18 |
申请号 |
US201313795036 |
申请日期 |
2013.03.12 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
Prabhakar Venkatraman;Shakeri Kaveh;Hinh Long;Puthenthermadam Sarath C. |
分类号 |
H01L27/07;H01L29/66 |
主分类号 |
H01L27/07 |
代理机构 |
|
代理人 |
|
主权项 |
1. A memory cell, comprising:
at least a first programmable section coupled between a first supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first access transistor, and a second S/D region shared with a second access transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region and a more graded dopant p-n junction than the second S/D region, and includes a first S/D region contained by a grade increasing region of the same conductivity type as the first S/D region and the programmable transistor has a charge storage structure formed between its control gate and its channel. |
地址 |
San Jose CA US |