Semiconductor Devices and Methods of Manufacturing the Same

摘要

A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

主权项

1. A memory device, comprising:
a plurality of semiconductor patterns on a substrate, each of the plurality of semiconductor patterns comprising a first region doped with impurities at a first concentration; a plurality of second regions at a plurality of first upper portions of the substrate, wherein each of the plurality of second regions contacts one of the plurality of semiconductor patterns and is doped with impurities at a second concentration; a plurality of channel patterns on the plurality of semiconductor patterns, wherein each of the plurality of channel patterns corresponds to a respective one of the plurality of semiconductor patterns and extends in a first direction substantially perpendicular to a top surface of the substrate; a plurality of gate structures, wherein each of the plurality of gate structures extends in a second direction substantially parallel to the top surface of the substrate and is adjacent to a sidewall of each of one or more of the plurality of channel patterns, and wherein the plurality of gate structures are spaced apart from each other in the first direction; a plurality of third regions at a plurality of second upper portions of the substrate adjacent to end portions of the plurality of gate structures, wherein each of the plurality of third regions is doped with impurities and is configured to provide a common source line; and a plurality of fourth regions at a plurality of third upper portions of the substrate between the second and third regions and between adjacent second regions, wherein each of the plurality of fourth regions is doped with impurities at a third concentration, and wherein the third concentration is lower than the first and second concentrations.