发明名称 |
SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT |
摘要 |
A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted. |
申请公布号 |
US2014282319(A1) |
申请公布日期 |
2014.09.18 |
申请号 |
US201313800751 |
申请日期 |
2013.03.13 |
申请人 |
Company, Ltd. Taiwan Semiconductor Manufacturing |
发明人 |
XU Shaojie;TANG Yukit;HOU Pao-Po;TAO Derek C.;LUM Annie-Li-Keow |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method of designing a semiconductor circuit, the semiconductor circuit comprising
an array of repeating blocks, each of the blocks comprising a device, and at least one signal line connecting the devices of the blocks, said method performed by at least one processor and comprising: generating a model of the semiconductor circuit, the model comprising a functional area corresponding to at least one first block among the blocks of the array, and a loading area corresponding to at least one second block among the blocks of the array; extracting, in the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block; and extracting, in the loading area, parasitic parameters of the at least one signal line, without extracting parasitic parameters of the device of the at least one second block. |
地址 |
US |