发明名称 CONDITIONAL LINKS FOR DIRECT MEMORY ACCESS CONTROLLERS
摘要 Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.
申请公布号 US2014281098(A1) 申请公布日期 2014.09.18
申请号 US201313803811 申请日期 2013.03.14
申请人 INFINEON TECHNOLOGIES AG 发明人 Hellwig Frank;Cottam Simon;Zweck Harald
分类号 G06F13/28 主分类号 G06F13/28
代理机构 代理人
主权项 1. A Direct Memory Access (DMA) controller, comprising: a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface; pattern comparison logic configured to compare the read pattern to at least one predetermined pattern; and control logic configured to induce the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and further configured to induce the bus controller to process a second conditional link over the system bus interface if the read pattern matches the predetermined pattern.
地址 Neubiberg DE