LOW-POWER AND ALL-DIGITAL PHASE INTERPOLATOR-BASED CLOCK AND DATA RECOVERY ARCHITECTURE

摘要

The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

主权项

1. A transceiver comprising:
a phase rotator (PR)-based delay-locked loop and phase-locked loop (D/PLL) unit configured to generate demultiplexed data samples for input data using multiphase clock signals for sampling the input data and a reference clock signal; and a multiplexer configured to serialize the demultiplexed data samples, wherein the multiphase clock signals are generated using a first clock signal, for retiming the sampled input data, controlled by the phase-locked loop (PLL) and a second clock signal controlled by the delay-locked loop (DLL).