发明名称 |
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME |
摘要 |
In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate. |
申请公布号 |
US2014264538(A1) |
申请公布日期 |
2014.09.18 |
申请号 |
US201414200274 |
申请日期 |
2014.03.07 |
申请人 |
YU Tea-Kwang;KWON Bae-Seong;KIM Yong-Tae;CHUNG Chul-Ho;CHOI Yong-Suk |
发明人 |
YU Tea-Kwang;KWON Bae-Seong;KIM Yong-Tae;CHUNG Chul-Ho;CHOI Yong-Suk |
分类号 |
H01L29/788;H01L21/28;H01L27/115;H01L29/66 |
主分类号 |
H01L29/788 |
代理机构 |
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代理人 |
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主权项 |
1. A method of manufacturing a semiconductor device, comprising:
forming a split gate structure on a cell region of a substrate, the substrate including the cell region in which memory cells are formed and a logic region in which logic elements are formed, the logic region having a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure including a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate; forming a spacer layer on the split gate structure and the substrate; etching the spacer layer to form a spacer and a second gate insulation layer pattern, the spacer being formed on a sidewall of the split gate structure and the second gate insulation layer pattern being formed on the ultra high voltage region of the substrate; and forming a gate electrode on the high voltage region, the second gate insulation layer pattern, and the low voltage region. |
地址 |
Hwaseong-si KR |