| 摘要 |
An aspect of the present embodiment, there is provided a semiconductor memory device including memory cell arrays, each of the memory cell arrays including memory cells, including a clock generator configured to generate clock, an input-output circuit configured to input and output data, buses, a portion of each of the buses crossing the memory cell arrays, switches, each of the switches being placed in the bus, control circuit configured to control the switches to generate a path which transfers clock and data without overlapping with an activated memory cell as viewed from above. |
