| 发明名称 |
BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL |
| 摘要 |
A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode. |
| 申请公布号 |
US2014281778(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201313967337 |
申请日期 |
2013.08.14 |
| 申请人 |
Ahmed Nisar;Jindal Anurag;Mahajan Nipun |
发明人 |
Ahmed Nisar;Jindal Anurag;Mahajan Nipun |
| 分类号 |
G01R31/3177 |
主分类号 |
G01R31/3177 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processing system, comprising:
a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode; and a plurality of shift-capture clock generator circuits, each shift-capture clock generator circuit including a clock gate circuit and a clock divider circuit, wherein: each of the shift-capture clock generator circuits is configured to receive a corresponding one of the plurality of clock signals, and at least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode. |
| 地址 |
Bee Cave TX US |
