SYNCHRONIZATION AND ORDER DETECTION IN A MEMORY SYSTEM

摘要

Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

主权项

1. A system for out-of-synchronization and out-of-order detection in a memory system, the system comprising:
a plurality of channels each providing communication with a memory buffer chip and a plurality of memory devices; and a memory control unit coupled to the plurality of channels, the memory control unit configured to perform a method comprising:
receiving frames on two or more of the channels;identifying, by the memory control unit, an alignment logic input in each of the received frames;generating, by the memory control unit, a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input;adjusting, by the memory control unit, a timing alignment of the summarized input for each of the channels of the received frames based on a skew value per channel;comparing each of the timing adjusted summarized inputs; andbased on a mismatch between at least two of the timing adjusted summarized inputs, asserting a miscompare signal by the memory control unit.