发明名称 METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION
摘要 The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.
申请公布号 US2014282308(A1) 申请公布日期 2014.09.18
申请号 US201313795220 申请日期 2013.03.12
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Chen Chin-Sheng;Yang Tsun-Yu;Hu Wei-Yi;Chung Tao Wen;Lee Hui Yu;Kuan Jui-Feng;Cheng Yi-Kan
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A design flow method, comprising: generating a schematic representation of a circuit with a schematic design tool; linking the schematic representation to a device library within a memory store with the schematic design tool, the device library comprising a set of passive design elements and a first set of functional parameters corresponding to the set of passive design elements, wherein the set of passive design elements and first set of functional parameters are represented in a pre-layout simulation format; instantiating a passive schematic design element of the set of passive design elements within the schematic representation with the schematic design tool; and performing a pre-layout simulation comprising simulating function of the schematic representation with a first functional parameter from the first set of functional parameters assigned to the passive schematic design element with a circuit simulation tool.
地址 Hsin-Chu TW