STRIDE-BASED TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING WITH ADAPTIVE OFFSET

摘要

A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.

主权项

1. A processing device, comprising:
a data prefetcher to generate a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request; a translation lookaside buffer (TLB) prefetch address computation component communicably coupled to the data prefetcher, the TLB prefetch address computation component to generate a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset; and a cross page detection component communicably coupled to the data prefetcher and the TLB prefetch address computation component, the cross page detection component to:
determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address; andcause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.