发明名称 |
EYE WIDTH MEASUREMENT AND MARGINING IN COMMUNICATION SYSTEMS |
摘要 |
Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected. |
申请公布号 |
US2014270030(A1) |
申请公布日期 |
2014.09.18 |
申请号 |
US201313836383 |
申请日期 |
2013.03.15 |
申请人 |
HAMMAD DIMA;LEVIN VADIM;LAUFER AMIR;BAR-LEV RON;FAMILIA NOAM;LEVIN ITAMAR |
发明人 |
HAMMAD DIMA;LEVIN VADIM;LAUFER AMIR;BAR-LEV RON;FAMILIA NOAM;LEVIN ITAMAR |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a controller module configured to decouple a phase detector from a loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal at a receiver clock signal frequency, the margining clock signal generated by an oscillator coupled to the loop filter; a margining input module configured to apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; a compare module configured to compare a first bit stream and a second bit stream, the comparing configured to detect an error, the first bit stream related to a transmitted bit stream received by the receiver under test; and a counter logic module configured to count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when an error is detected. |
地址 |
Jerusalem IL |