DATA SYNCHRONIZATION ACROSS ASYNCHRONOUS BOUNDARIES USING SELECTABLE SYNCHRONIZERS TO MINIMIZE LATENCY

摘要

A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first clock domain and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain. The synchronizer sub-unit includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers.

主权项

1. A apparatus, comprising:
a unit associated with a first clock domain; and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain, wherein the SSU includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers.