| 发明名称 |
PRIORITY BASED LAYOUT VERSUS SCHEMATIC (LVS) |
| 摘要 |
An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices. |
| 申请公布号 |
US2014282330(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201313837763 |
申请日期 |
2013.03.15 |
| 申请人 |
GLOBALFOUNDRIES INC. |
发明人 |
MOJUMDER Niladri;Paul Bipul;Mittal Anurag;Werner Juengling |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
determining a first electrical layout indicating an electrical performance of a physical layout of an integrated circuit (IC) design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices. |
| 地址 |
Grand Cayman KY |
