发明名称 NON-VOLATILE MEMORY (NVM) WITH WORD LINE DRIVER/DECODER USING A CHARGE PUMP VOLTAGE
摘要 A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.
申请公布号 US2014269140(A1) 申请公布日期 2014.09.18
申请号 US201313826958 申请日期 2013.03.14
申请人 SANJEEVARAO PADMARAJ;CHRUDIMSKY DAVID W. 发明人 SANJEEVARAO PADMARAJ;CHRUDIMSKY DAVID W.
分类号 G11C5/14;G11C8/08 主分类号 G11C5/14
代理机构 代理人
主权项 1. A word line driver comprising: a first stack of transistors, the first stack including: a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals;a cascode transistor having a first current electrode connected to the first node, the cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage;a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the cascode transistor; a pull up transistor having a first current electrode coupled to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode coupled to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage; and an inverting circuit including an input and an output, the input is coupled to the second node, wherein inverting circuit provides at its output, and inverted logic state of the second node; wherein the plurality of decode transistors are characterized as lower voltage transistors; and wherein the third transistor is characterized as a higher voltage transistor.
地址 Austin TX US