STRUCTURE AND FABRICATION OF MEMORY ARRAY WITH EPITAXIALLY GROWN MEMORY ELEMENTS AND LINE-SPACE PATTERNS

摘要

A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

主权项

1. A memory array device comprising:
a plurality of memory cells, each memory cell including:
(a) a field effect transistor (FET) over a substrate; and(b) a memory element electrically coupled to the FET, the memory element including a plurality of memory element layers wherein the memory element layers are epitaxially grown directly on top of the FET; a plurality of gate conductors configured along a first axis in parallel, wherein each FET of the memory cells is adjacent to two gate conductors; and a plurality of bit lines configured along a second axis in parallel, wherein each bit line is electrically coupled to a plurality of memory elements of the memory cells along the second axis, the second axis being perpendicular to the first axis.