NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS

摘要

A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.

主权项

1. A method of forming a semiconductor structure comprising:
forming an alternating stack of a first semiconductor material and a second semiconductor material on a substrate; patterning said alternating stack to form a patterned stack including a nanowire-including region, a first pad region adjoining said nanowire-including region, and a second pad region adjoining said nanowire-including region and spaced from said first pad region; removing said second semiconductor material selective to said first semiconductor material, wherein said nanowire-including region includes semiconductor nanowires containing said first semiconductor material and suspended between said first pad region and said second pad region, and does not include said second semiconductor material, and said first and second pad regions include second semiconductor material pad portions having sidewalls that are laterally recessed from sidewalls of first semiconductor material pad portions; forming a gate electrode structure straddling said semiconductor nanowires; forming a gate spacer around said gate electrode structure; and forming a raised source region and a raised drain region by depositing a semiconductor material on physically exposed surfaces of said semiconductor nanowire and said first and second pad regions.