发明名称 MULTIPHASE CLOCK GENERATION CIRCUIT AND CLOCK GENERATION METHOD FOR THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a multiphase clock generation circuit and a clock generation method therefor which generate a high accuracy multiphase clock by suppressing a random variation.SOLUTION: According to an embodiment, a multiphase clock generation circuit 10 includes a phase interpolation circuit 13-1 for generating a phase interpolation clock interpolating phases between two reference clocks different in phase, and a boost-enabled buffer circuit 15-1 for driving the phase interpolation clock generated by the phase interpolation circuit 13-1 with a gain set on the basis of the frequency of the phase interpolation clock.
申请公布号 JP2014171039(A) 申请公布日期 2014.09.18
申请号 JP20130040957 申请日期 2013.03.01
申请人 NEC CORP 发明人 NEDACHI TAKAAKI
分类号 H03K5/15 主分类号 H03K5/15
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