Method for Reducing Effective Raw Bit Error Rate in Multi-Level Cell NAND Flash Memory

摘要

A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

主权项

1. A memory system comprising:
a flash subsystem grouped into pages of data, the pages of data including error correcting code (ECC) and being identified by page numbers, at least some of the pages of data having a lower page of data and an upper page of data, wherein the lower and upper pages of data are paired together; a flash controller coupled to the flash subsystem, the flash controller configured to split the ECC; and a buffer including a page of data from the at least some of the page of data, the page of data having an upper page of data and a lower page of data and to be programmed into the flash subsystem, wherein at least a segment of the upper page of data or at least a segment of the lower page of data is concatenated with a split ECC.