| 发明名称 |
INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME |
| 摘要 |
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap. |
| 申请公布号 |
US2014264903(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201313796499 |
申请日期 |
2013.03.12 |
| 申请人 |
Company, Ltd. Taiwan Semiconductor Manufacturing |
发明人 |
Chen Jeng-Shiou;Ting Chih-Yuan;Shieh Jyu-Horng;Tsai Minghsing |
| 分类号 |
H01L23/532;H01L21/768 |
主分类号 |
H01L23/532 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An interconnect structure, comprising:
a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap. |
| 地址 |
US |
