SYSTEM AND METHOD FOR A HYBRID CLOCK DOMAIN CROSSING VERIFICATION

摘要

A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage. Results are then reiterated through the system back to the static CDC verification.

主权项

1. A method implemented in a programmable system for performing hybrid clock domain crossing (CDC) verification of a circuit design of at least a portion of an integrated circuit, the method comprising:
receiving into the system a description of the circuit; performing static CDC verification from the received description; generating from the received description a set of assertions and monitors respective of the circuit; performing a simulation of the circuit based on the generated assertions and monitors; and storing in memory accessible by the system at least one of: results of the CDC verification, the assertions and monitors, and results of the simulation.