发明名称 COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING LOGIC
摘要 An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.
申请公布号 US2014281419(A1) 申请公布日期 2014.09.18
申请号 US201313840363 申请日期 2013.03.15
申请人 Intel Corporation 发明人 Lupon Marc;Magklis Grigorios;Samudrala Sridhar;Martinez Raul;Stavrou Kyriakos A.;Codina Enric Gibert
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
主权项 1. An error handling method, comprising: identifying a code region eligible for cumulative multiply add (CMA) optimization; translating code region instructions into interpreter code instructions, including translating sequences of multiply add instructions in the code region instructions into fusion code comprising CMA instructions; executing the interpreter code instructions, including executing the fusion code; monitoring floating point (FP) exceptions generated by the fusion code; and retranslating at least a portion of the code region instructions to eliminate the fusion code from the portion of the code region responsive to receiving a number of CMA intermediate rounding exceptions exceeding a predetermined threshold.
地址 Santa Clara CA US