| 发明名称 |
PROCESSORS, METHODS, AND SYSTEMS TO RELAX SYNCHRONIZATION OF ACCESSES TO SHARED MEMORY |
| 摘要 |
A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode. |
| 申请公布号 |
US2014281196(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201313844729 |
申请日期 |
2013.03.15 |
| 申请人 |
Dixon Martin G.;Rash William C.;Santiago Yazmin A. |
发明人 |
Dixon Martin G.;Rash William C.;Santiago Yazmin A. |
| 分类号 |
G06F12/14 |
主分类号 |
G06F12/14 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
a plurality of logical processors; a first logical processor of the plurality, the first logical processor to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory; and memory access synchronization relaxation logic to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode. |
| 地址 |
Portland OR US |
